The above referenced related patent applications disclose semiconductor devices, such as gallium nitride (GaN) semiconductor power devices, using an island electrode topology.
For example, as disclosed in the above referenced co-pending U.S. patent application Ser. No. 13/020,712, entitled “Gallium nitride power devices using island topography”, GaN transistors with ultra-low on-resistance can be produced using Island Topology™. This particular island electrode topology provides a compact structure with a gate width more than double that of a conventional multi-finger design of a similar device size, with superior current handling per unit area. A breakdown voltage exceeding 1200V can be achieved.
Faults or defective areas may, for example, be caused by defects in the semiconductor layer, e.g. caused by faults in the growth of gallium nitride on a silicon substrate, which has a different crystal structure. While GaN may be grown on some substrates, e.g. SiC, with lower defect densities, it is desirable to be able to use less expensive GaN-on-silicon substrates, which are known to have a higher defect density per unit area.
A fault in the active channel region of a conventional large gate width, multi-finger GaN transistor design, such as shown in FIG. 1B, can cause failure of the entire device. As the device area increases, and depending on the defect density in active regions of the GaN semiconductor layer, the probability of one or more faults or defects increases.
As disclosed in U.S. patent application Ser. No. 13/020,712, in a GaN transistor using Island Topology™, such as illustrated in FIGS. 2A and 2B, it is possible to isolate defective areas, i.e., by disconnection of the gate strap from a gate electrode element in a defective area. If needed, a disconnected gate element may also be grounded to the source electrode. Where bump connections are used to the source and/or drain electrodes, individual source or drain island electrodes may be electrically isolated by removing individual bump connections in defective regions. Thus, an island electrode topology provides the ability to isolate faults or defective areas. Nevertheless, for a semiconductor layer having a particular defect density per unit area, as the device area increases, the probability of finding a defect in the device area increases accordingly. FIG. 3 shows a graph illustrating an example of die yield vs. device size for a conventional design of a GaN semiconductor transistor having a large gate width Wg, such as shown in FIG. 1.
As will be described in more detail below, in view of the degree of interconnection of the gate electrodes in this structure, and the gate width per gate connection, disconnection of only one gate contact significantly decreases the overall gate width Wg of the device. For example, for a defective middle gate connection, its removal or isolation effectively deactivates 7 adjacent sets of source/drain and gate connections. In such an arrangement, for a multi-island device fabricated on a GaN-on-silicon wafer, the yield of devices having an acceptable gate width Wg may be low, depending on the defect density per unit area of the substrate wafer.
Moreover, for large gate width transistors using a large number of island electrodes, it will be apparent that it becomes complex and time consuming to electrically test each element separately, i.e., to electrically test each source island, drain island and gate electrode combination, to find defective elements or defective areas of the semiconductor layer.
Thus, it would be desirable to provide systems and devices based on an island topology, which provide improved fault tolerance and/or which facilitate electrical testing for defect detection and mitigation.
The present invention seeks to overcome, or mitigate, one or more of the above mentioned limitations of these known systems and devices using an island topology, or at least provide an alternative.